1. Field of the Invention
The present invention relates to a row address strobe signal input buffer of a semiconductor memory device and, more particularly, to a row address strobe signal input buffer for receiving a row address strobe signal of a TTL (Transistor-Transistor Logic) level and generating an internal signal of a CMOS (Complementary Metal Oxide Semiconductor) level.
2. Description of the Related Art
In a dynamic random access memory (DRAM), a row address strobe signal input buffer is a circuit for converting a row address strobe signal RAS which is an externally applied chip enable signal, into a chip internal signal. The row address strobe signal RAS is externally supplied to the row address strobe signal input buffer at a TTL level and converted into the internal signal of a CMOS level, enabling the DRAM. That is, when the row address strobe signal RAS is changed from logic "HIGH" to logic "LOW", it drives the row address strobe signal input buffer which generates a signal that activates the DRAM. However, since the row address strobe signal RAS is not a signal of the CMOS level, the output state of the row address strobe signal input buffer may fluctuate due to power noise generated within the DRAM. In other words, the output of the row address strobe signal input buffer may be affected by various power noise sources within a chip, such as bit line sensing noise, data output noise, etc. The affected output of the row address strobe signal input buffer leads to a glitch in the signal level of the internal signal.
FIG. 1 is a circuit diagram of a conventional row address strobe signal input buffer. An inverter I1 receives a power-up reset signal VCCH. A PMOS transistor T1 supplies a voltage of logic "HIGH" to the source of a PMOS transistor T2 in response to an output signal of the inverter I1. The PMOS transistor T2 and an NMOS transistor T3 having the channels serially connected between the drain of the transistor T1 and a ground voltage termin RASal constitute an inverter and generate an inverted output of the row address strobe signal. An NMOS transistor T4 has the gate connected to the output signal of the inverter I1 and has the channel connected between a node N1 and the ground voltage terminal. Inverters I2 and I3 are serially connected between the node N1 and an internal signal PR. The transistors T1-T4 are a circuit having the construction of a NOR gate.
In operation, the power-up reset signal VCCH is used for cutting off the operation of internal circuits of a semiconductor memory device until VCCH is raised to a predetermined level, about 2 V for instance. When VCCH is changed from logic "LOW" to logic "HIGH" its activated state, the row address strobe signal input buffer is initialized. Once the circuit is initialized the internal signal PR in response to the row address strobe signal RAS. In the initialized state, if the row address strobe signal RAS is changed from logic "HIGH" to logic "LOW," its activated state, the internal signal PR is changed from logic "LOW" to logic "HIGH," its enabled state. However, as shown in FIG. 2, a timing chart of the signals indicated in FIG. 1, during the activated interval of the row address strobe signal RAS, if the row address strobe signal RAS is sensed as logic "HIGH" by the power noise within the chip, such as the bit line sensing noise, data output noise, etc., the node N1 is inverted from logic "HIGH" to logic "LOW," and the internal signal PR is changed from logic "HIGH" to logic "LOW," its disabled state. This sequence of events causes a glitch in the internal signal.